1. Field of the Invention
The invention relates in general to an ONO formation of semiconductor memory device and method of fabricating the same, and more particularly to the method of forming the ONO and bit lines of semiconductor memory device.
2. Description of the Related Art
Non-volatile memory devices have been widely used in the electronic products. The memory device is programmed by inducing hot electrons injection from the substrate to the ONO dielectric. The ONO dielectric generally has a silicon nitride layer sandwiched between a bottom oxide layer and a top oxide layer. The silicon nitride layer provides a charge trapping mechanism for programming the memory cell. Many researches about ONO formation of non-volatile memory device have been published in the recent years.
Referring to FIG. 1A˜1D, a conventional method of forming the ONO dielectric and bit lines of the non-volatile memory device is illustrated. This conventional method is disclosed in U.S. Pat. No. 6,436,768 to Yang et al. First, a substrate 10 on which a bottom oxide layer 11 and silicon nitride layer 12 are deposited is provided, as shown in FIG. 1A. Then, a patterned photoresist (PR) is formed above the silicon nitride layer to expose the doped regions, as shown in FIG. 1B. After the PR layer is patterned, ions are implanted into the substrate 10, as shown by the arrows, forming the doped regions 101 of FIG. 1C. The implantation is conducted to achieve a suitable dosage. The doped regions 101 functions as the bit lines of the memory device. The semiconductor structure is annealed at a suitable temperature after implantation. After annealing, a top oxide layer 16 is formed on the silicon nitride layer 12 for completing the formation of ONO dielectric, as shown in FIG. 1D.
However, the method described by Yang et al. requires a high concentration and high energy of dosage during ion implantation. Examples of implanted dosage includes a range from about 1×1014 to about 1×1016 atoms/cm2, a range from about 5×1014 to about 7×1015 atoms/cm2, and a range from about 1×1015 to about 5×1015 atoms/cm2. The implant energy can be as high as 100 keV. Unfortunately, the ion implantation through the NO (i.e. nitride-oxide) stack damages the silicon nitride layer and the bottom oxide layer, thereby causing the interface traps between the bottom oxide layer and the silicon nitride layer. Also, the ions rebounded from the doped regions could randomly impact the bottom oxide layer during implantation, resulting in a severer damage to the bottom oxide layer and leading to charge loss through the bottom oxide layer. Although the annealing process is performed after implantation and most portion of silicon nitride layer and the bottom oxide have been repaired, the interface traps are hardly recovered (since oxygen is hardly penetrate the bottom oxide layer through the silicon nitride layer).
FIG. 2A˜2D illustrate a cross-sectional view of another conventional method of forming the ONO dielectric and bit lines of the non-volatile memory device. This conventional method is disclosed in U.S. Pat. No. 6,803,279 to Eitan et al. First, a substrate 20 on which a bottom oxide layer 21, silicon nitride layer 22 and a top oxide layer 23 are formed is provided, as shown in FIG. 2A. Then, a patterned photoresist (PR) 24 is formed above the top oxide layer 23 to expose the doped regions, as shown in FIG. 2B. Before implanting the bit lines, at least the top oxide layer 23 and the silicon nitride layer 22 are etched according to the patterned PR 24, for the purpose of decreasing the energy of implanted dosage. In FIG. 2C, the top oxide layer 23, the silicon nitride layer 22 and the bottom oxide layer 21 uncovered by the patterned PR 24 are etched away. Then, ions are implanted into the substrate, as shown by the arrows, forming the doped regions 201 of FIG. 2C. The doped regions 201 functions as the bit lines of the memory device. After implantation, the patterned PR 24 is removed and BD (i.e. formed about the bit lines) oxides 25 are then thermally grown in an oxidation operation. The BD oxides 25 are typically very thick, as shown in FIG. 2D.
According to the method disclosed by Eitan et al., bit line formation is performed after ONO dielectric is opened; thus, the ion implantation can still cause serve damage to the bottom oxide layer, thereby leading the charge loss of the memory device. ONO dielectric breakdown is easily occurred at the junctions between the BD oxides and the adjacent ONO stacks. Also, hydrogen can penetrate the interface between the bottom oxide layer and silicon nitride layer through the BD oxides, causing a bad retention performance of memory device.